In an embedded processor based system, it is common to store data and program code in an on-chip read only memory (ROM). Such on-chip ROM has a low area and is non-volatile. Making any modifications in the ROM contents requires the chip to be re-manufactured. For some program changes, such as functional enhancements, chips with new ROMs can be used in a next generation product. For critical functional failures, the system must be recalled from the customer and the new chips substituted for the prior chips. This can be very expensive.
Previous solutions to this problem include: U.S. Pat. No. 4,028,678, U.S. Pat. No. 4,028,679, U.S. Pat. No. 4,028,683, U.S. Pat. No. 4,028,684, U.S. Pat. No. 4,400,798, U.S. Pat. No. 4,542,453, U.S. Pat. No. 4,610,000 and the paper “Patchable Instruction ROM Architecture” by Sherwood and Calder, in the conference CASES '01, Nov. 16-17, 2001, Atlanta, Ga., USA.
All of these prior solutions patch ROM contents on a location by location basis. This is useful for defect masking in ROM designs as in the first few patents, or in microcode patches as in some of the other patents. However, application code patches are typically larger in size than enabled by these techniques. Location wise patching is not effective in such cases. The best one can do is use the patch to branch to patch code elsewhere in the system. This both increases access latency and reduces performance. Most of these prior solutions rely on either chip pin level controls or associative look-up tables to detect the access to be patched. These techniques are either expensive solutions that negatively impact access time or compatibility. Pin based controls are particularly bad for compatibility. None of these prior solutions deal with multi-level memory systems.